Paper Clock Multiplication Techniques Using Digitial Multiplying Delay-Locked-Loops

From Amr Elshazly’s Paper

Introduction

A classical digital PLL composed of TDC, digital loop filter (DLF) and DCO (possibly DAC followed by VCO).

Digital Multiplying DLL is different from classical digital PLL, in terms of noise transfers and many other things.

Overview of Multiplying Delay-Locked Loops

Unlike classical PLLs, MDLLs in a sense remove jitter accumulation by edge realignment. Sheng Ye’s paper shows edge relaignment can effectively remove phase noise up to about \(2 \omega_{loop}\) instead of \(\omega_{loop}\) by high-pass filtering.