Coupling Effects
ISSCC 2024
Session 10: Frequency Synthesis
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
- conventional variable slope dtc its linearity is limited by the slope-dependent propagation delay of the output buffer (comparator).
- in practice, variable slope dtc can be implemented as rc delay, the delay is defined by the rc constant, thus it is linear with respect to either r or c. The slope dependent comparator delay can be mitigated by adding a fixed capacitance to reduce the slope variation. However, as discussed in the slides, adding fixed capacitance increases power and jitter.
- In this paper, by adding a tail resistor to intentionally introduce an upward concavity nonlinear, the overall nonlinear can be reduced by combining the two different concavity.
10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm
- for multi-variable lms calibration, the steps for different control should be much larger or smaller to avoid racing. As a result, the smallest step will suffer slow convergence.
- proposed recursive-least-square, with dichotomous coordinate descent-based recursive-least-square, achieve fast convergence with small hardware complexity.
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter
- The proposed cascaded fractional divider, isn’t it the same as fcw subtractive dithering?
- It doesn’t compare fractional spur with fcw subtractive dithering.
- use differential dtc (why it is called “pseudo differential”)? Isn’t differential dtc has been implemented?
10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs
- prior art: successive requantizer, probability mass redistributor, time-invariant probability modulator, probability density shaping, enhanced nonlinear-induced noise performance.
- another technique to mitigate fractional spur.
10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
- constant-slope dtc or inverse constant-slope dtc increases thermal noise due to long pre-charge time (limited voltage slope).
ISSCC 2023
Session 32: Intelligent Biomedical Circuits and Systems
32.1 A Behind-The-Ear Patch-Type Mental Healthcare Integrated Interface with 275-Fold Input Impedance Boosting and Adaptive Multimodal Compensation Capabilities
- Battery
- Behind-The-Ear
- ExG,PPG,GSR,BIOZ,tVNS
32.7 Fascicle-Selective Bidirectional Peripheral Nerve Interface IC with 173dB FOM Noise-Shaping SAR ADCs and 1.38pJ/b Frequency-Multiplying Current-Ripple Radio Transmitter
- Ultrasound Power
- Nerve Cuff Electrodes
ISSCC 2022
Session 12: Monolithic System for Robot and Bio Applications
Session 20: Body and Brain Interfaces
20.5 A Miniaturized Wireless Neural Implant with Body-Coupled Data Transmission and Power Delivery for Freely Behaving Animals
- Body-Coupled Communication
- Body-Coupled Power Delivery